题  目：Cross-Layer Energy Efficient Accelerator Design and Optimization: From System to FPGA Implementation 
报告人：卓成 教授
时  间：2018年4月12日（周四）下午14:30-16:30
地  点：研究院1号楼618室

Abstract
With Moore’s Law approaching sub-7nm, CMOS scaling trend is slowing down. Conventional Von Neumann architecture suffers from multiple bottlenecks and hence becomes energy inefficient especially for data intensive or AI applications. Thus, there is an increasing interest in new device, architectures, algorithms and computational models for energy-efficient accelerator design. While such advancements demonstrate quite unique and promising characteristics, the discussions are usually limited to its own design layer. The lack of coordination between software and hardware, host CPU and accelerator, or architecture and circuit/device may mitigate the potential of those new technologies and even hurt the overall performance of the system. Thus, how to co-ordinate various devices and conduct cross-layer optimization become a very challenging problems for energy-efficient accelerator design. This talk will discuss two key aspects, (1) A simulation framework that enables the coordination and co-optimization between host CPU and accelerator; (2) Mutli-layer optimization of a neural network accelerator with a new architecture, where we employ FPGA implementation as an example.

Biography
    卓成教授于2005年和2007年自浙江大学获得学士和硕士学位，2010年自密歇根大学-安娜堡获得博士学位。2011年至2016年在美国英特尔公司负责先进互连及低功耗优化等工作，2017年日本大阪大学客座教授。主要研究领域为低功耗架构及加速器，3D芯片以及高能效神经网络设计，具有多年研究和工业界相关经验，荣获ACM SIGDA技术领袖奖，2016年DAC最佳论文提名奖， 2017年JSPS Invitation Fellowship，以及2018年CSTIC最佳学生论文提名。受邀现任IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems（CCF-A）编委，IEEE VLSI Circuits and Systems Letter编委， Elsevier Integration, the VLSI Journal编委。现任或曾任多个业内顶级会议的技术委员会及组织委员会成员，为IEEE高级会员。

联系人：王新胜